TABLE OF CONTENTS
1. INTRODUCTION
Features 1-1
Design Goals 1-2
Nomenclature 1-2
2. REGISTER AND STACK USAGE
Register Names 2-1
Register Functions 2-1
Figure 2-1. DATA AND PROGRAM REGISTERS 2-2
Stack Usage 2-3
Figure 2-2. STACK STRUCTURE 2-4
Register Access Method 2-5
Figure 2-3. SIMPLE EXTERNAL CIRCUITRY FOR REGISTER 2-6 2-7
3. PROGRAM STATUS WORD (PSW)
Contents of the PSW 3-1
Use of PSW Bits 3-2
Interrupt Process 3-2
Figure 3-1. PSW Bits 3-3
4. INTERRUPT AND INPUT/OUTPUT OPERATION
Sequence of Events During an Interrupt 4-1
Register Allocation During Interrupts 4-1
Input/Output Data Transfer 4-2
Interrupt Signals 4-3
Interrupt Microinstruction Sequence 4-3
Figure 4-1. INTERRUPT SIGNALS 4-4
Figure 4-2. INTERRUPT SIGNAL TIMING 4-5
Minimum Interrupt Routine Utilizing BYTEIN/BYTEOUT 4-6
INSTRUCTIONS
Priority Systems For Multiple Interrupt Levels 4-6
Figure 4-3. MICROINSTRUCTIONS USED IN A BYTEIN 4-7
INTERRUPT ROUTINE
BLOCKIN And BLOCKOUT Instructions 4-8
TABLE OF CONTENTS (continued)
5. INSTRUCTIONS
Alignment Rules 5-1
Arithmetic and Logic Methods 5-1
Cycle Times 5-1
Figure 5.1 METHODS FOR SUBTRACT, SHIFT LEFT 5-2
AND LOGICAL OR
Mnemonics 5-3
Table 5-1. ABO MICROCOMPUTER INSTRUCTIONS 5-4
5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12
6. ELECTRICAL CHARACTERISTICS
MOS Characteristics 6-1
Power Supply 6-1
Table 6-1. VOLTAGE SPECIFICATIONS OF INPUT AND 6-2
OUTPUT SIGNALS
Figure 6-1. CONNECTIONS TO ABO MICROCOMPUTER 6-3
Input Signals 6-4
Output Signals 6-4
Clock Inputs 6-4 6-5
Dynamic Storage 6-6
Figure 6-2. CLOCK TIMING 6-7
7. INTERNAL OPERATION
Internal Data Paths and Registers 7-1
Typical Instruction Execution 7-1
TROM And ROM Address Registers 7-1
Table 7-1. MAJOR COMPONENTS OF THE ABO 7-2
MICROCOMPUTER
Figure 7-1. ABO MICROCOMPUTER INTERNAL STRUCTURE 7-3 7-4
Figure 7-2. ADDRESS FORMATION IN THE ROM ADDRESS 7-5
REGISTER (RAR)
Figure 7-3. TROM Bits 7-6
Figure 7-4. SELECTION OF REGISTER ADDRESS FROM 7-6
I REGISTER
Microinstruction ROM 7-7
Figure 7-5. DATA PATHS FOR ARITHMETIC AND LOGIC 7-8
OPERATIONS
ALU And OP Register 7-9
Figure 7-6. DATA INPUT/OUTPUT CONTROL 7-10
PSW Register 7-11
Data Input/Output 7-11
Figure 7-7. TIMING OF EVENTS DURING ALU OPERATIONS 7-12
ADD2ND Microcycles 7-13
TABLE OF CONTENTS (continued)
7. (Continued)
Figure 7-8. MEMORY ADDRESSING LOGIC 7-14
Memory Addressing 7-15 7-16
Table 7-2. DECODING OF MICROINSTRUCTION 7-17
MAS FIELD
Figure 7-9. TIMING DURING INCREMENT OF CPC 7-18
REGISTER
CPC Register 7-19
Conditional Microinstruction Jumps 7-19
Figure 7-10. MICROINSTRUCTION CONDITIONAL JUMP 7-20 7-21
LOGIC SIGNALS
MICROPROGRAMMING RULES
Creating New Microinstructions 8-1
CPC Field 8-1
JC Field 8-2
MAS Field 8-2
MI Field 8-2
Table 8-1. MICROINSTRUCTION FORMAT 8-3
ALU Field 8-4
SETC Field 8-4
SETCC Field 8-4
ZS Field 8-5
ZD Field 8-5
ADDRESS Field 8-6
Assigning ROM addresses and TROM Data 8-6
APPENDICES
A1 SUMMARY OF INPUT AND OUTPUT SIGNALS A1-1 A1-2
A2 GLOSSARY OF TERMS A2-1
A2-2 A2-3 A2-4 A2-5 A2-6
A3 LOGISPEC PROGRAM LOGIC EQUATIONS A3-1
A3-2 A3-3 A3-4 A3-5 A3-6 A3-7
A3-8 A3-9 A3-10 A3-11 A3-12 A3-13
A3-14 A3-15 A3-16 A3-17 A3-18 A3-19
A3-20 A3-21 A3-22 A3-23
A4 USE OF THE SENSE' INPUT A4-1 A4-2
A5 CONTENTS OF TROM AND MICROINSTRUCTION ROM A5-1
Figure A5-1, TROM CONTENTS A5-2
A5-3 A5-4 A5-5 A5-6 A5-7 A5-8
A5-9 A5-10
A6 MICROINSTRUCTION DESCRIPTION OF EACH INSTRUCTION A6-1
A6-2 A6-3 A6-4 A6-5 A6-6 A6-7
A6-8 A6-9 A6-10 A6-11 A6-12